NXP Semiconductors /LPC18xx /GPDMA /C2CONTROL

Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller.

Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.

0 (SOURCE_BURST_1): Source burst size = 1

1 (SOURCE_BURST_4): Source burst size = 4

2 (SOURCE_BURST_8): Source burst size = 8

3 (SOURCE_BURST_16): Source burst size = 16

4 (SOURCE_BURST_32): Source burst size = 32

5 (SOURCE_BURST_64): Source burst size = 64

6 (SOURCE_BURST_128): Source burst size = 128

7 (SOURCE_BURST_256): Source burst size = 256

Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.

0 (DESTINATION_BURST_1): Destination burst size = 1

1 (DESTINATION_BURST_4): Destination burst size = 4

2 (DESTINATION_BURST_8): Destination burst size = 8

3 (DESTINATION_BURST_16): Destination burst size = 16

4 (DESTINATION_BURST_32): Destination burst size = 32

5 (DESTINATION_BURST_64): Destination burst size = 64

6 (DESTINATION_BURST_128): Destination burst size = 128

7 (DESTINATION_BURST_256): Destination burst size = 256

Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.

0 (BYTE_8_BIT): Byte (8-bit)

1 (HALFWORD_16_BIT): Halfword (16-bit)

2 (WORD_32_BIT): Word (32-bit)

Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.

0 (BYTE_8_BIT): Byte (8-bit)

1 (HALFWORD_16_BIT): Halfword (16-bit)

2 (WORD_32_BIT): Word (32-bit)

Source AHB master select:

0 (AHB_MASTER_0_SELECTE): AHB Master 0 selected for source transfer.

1 (AHB_MASTER_1_SELECTE): AHB Master 1 selected for source transfer.

Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.

0 (AHB_MASTER_0_SELECTE): AHB Master 0 selected for destination transfer.

1 (AHB_MASTER_1_SELECTE): AHB Master 1 selected for destination transfer.

Source increment:

0 (NOT_INCREMENT): The source address is not incremented after each transfer.

1 (INCREMENT): The source address is incremented after each transfer.

Destination increment:

0 (THE_DESTINATION_ADDR): The destination address is not incremented after each transfer.

1 (THE_DESTINATION_ADDR): The destination address is incremented after each transfer.

Indicates that the access is in user mode or privileged mode:

0 (ACCESS_IS_IN_USER_MO): Access is in user mode

1 (ACCESS_IS_IN_PRIVILE): Access is in privileged mode.

Indicates that the access is bufferable or not bufferable:

0 (ACCESS_IS_NOT_BUFFER): Access is not bufferable.

1 (ACCESS_IS_BUFFERABLE): Access is bufferable.

Indicates that the access is cacheable or not cacheable:

0 (ACCESS_IS_NOT_CACHEA): Access is not cacheable.

1 (ACCESS_IS_CACHEABLE_): Access is cacheable.

Terminal count interrupt enable bit.

0 (THE_TERMINAL_COUNT_I): The terminal count interrupt is disabled.

1 (THE_TERMINAL_COUNT_I): The terminal count interrupt is enabled.